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600 ma/1000 ma, 2.5 mhz buck-boost dc-to-dc converters adp2503/adp2504 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2010 analog devices, inc. all rights reserved. features features 1 mm height profile 1 mm height profile compact pcb footprint compact pcb footprint seamless transition between modes seamless transition between modes 38 a typical quiescent current 38 a typical quiescent current 2.5 mhz operation enables 1.5 h inductor 2.5 mhz operation enables 1.5 h inductor input voltage: 2.3 v to 5.5 v input voltage: 2.3 v to 5.5 v fixed output voltage: 2.8 v to 5.0 v fixed output voltage: 2.8 v to 5.0 v adjustable model output voltage range: 2.8 v to 5.5 v adjustable model output voltage range: 2.8 v to 5.5 v 600 ma (adp2503) and 1000 ma (adp2504) output options 600 ma (adp2503) and 1000 ma (adp2504) output options boost converter configuration with load disconnect boost converter configuration with load disconnect sync pin with three different modes sync pin with three different modes power save mode (psm) for improved light load efficiency power save mode (psm) for improved light load efficiency forced fixed frequency operation mode forced fixed frequency operation mode synchronization with external clock synchronization with external clock internal compensation internal compensation soft start soft start enable/shutdown logic input enable/shutdown logic input overtemperature protection overtemperature protection short-circuit protection short-circuit protection undervoltage lockout protection undervoltage lockout protection small 10-lead 3 mm 3 mm lfcsp (qfn) package small 10-lead 3 mm 3 mm lfcsp (qfn) package applications applications wireless handsets wireless handsets digital cameras/portable audio players digital cameras/portable audio players miniature hard disk power supplies miniature hard disk power supplies usb powered devices usb powered devices general description general description the adp2503/adp2504 are high efficiency, low quiescent current step-up/step-down dc-to-dc converters that can operate at input voltages greater than, less than, or equal to the regulated output voltage. the power switches and synchronous rectifiers are internal to minimize external part count. at high load currents, the adp2503/adp2504 use a current-mode, fixed frequency pulse-width modulation (pwm) control scheme for optimal stability and transient response. to ensure the longest battery life in portable applications, the adp2503/adp2504 have an optional power save mode that reduces the switching frequency under light load conditions. for wireless and other low noise applica- tions where variable frequency power save mode may cause interference, the logic control input sync forces fixed frequency pwm operation under all load conditions. the adp2503/adp2504 are high efficiency, low quiescent current step-up/step-down dc-to-dc converters that can operate at input voltages greater than, less than, or equal to the regulated output voltage. the power switches and synchronous rectifiers are internal to minimize external part count. at high load currents, the adp2503/adp2504 use a current-mode, fixed frequency pulse-width modulation (pwm) control scheme for optimal stability and transient response. to ensure the longest battery life in portable applications, the adp2503/adp2504 have an optional power save mode that reduces the switching frequency under light load conditions. for wireless and other low noise applica- tions where variable frequency power save mode may cause interference, the logic control input sync forces fixed frequency pwm operation under all load conditions. the adp2503/adp2504 can run from input voltages between 2.3 v and 5.5 v, allowing single lithium or lithium polymer cell, multiple alkaline or nimh cells, pcmcia, usb, and other stan- dard power sources. the adp2503/adp2504 have fixed output options, or using the adjustable model, the output voltage can be programmed through an external resistor divider. compensa- tion is internal to minimize the number of external components. the adp2503/adp2504 can run from input voltages between 2.3 v and 5.5 v, allowing single lithium or lithium polymer cell, multiple alkaline or nimh cells, pcmcia, usb, and other stan- dard power sources. the adp2503/adp2504 have fixed output options, or using the adjustable model, the output voltage can be programmed through an external resistor divider. compensa- tion is internal to minimize the number of external components. during logic-controlled shutdown, the input is disconnected from the output and draws less than 1 a from the input source. operating as boost converters, the adp2503/adp2504 feature a true load disconnect function that isolates the load from the power source. other key features include undervoltage lockout to prevent deep battery discharge, and soft start to prevent input current overshoot at startup. during logic-controlled shutdown, the input is disconnected from the output and draws less than 1 a from the input source. operating as boost converters, the adp2503/adp2504 feature a true load disconnect function that isolates the load from the power source. other key features include undervoltage lockout to prevent deep battery discharge, and soft start to prevent input current overshoot at startup. typical application circuit typical application circuit sw1 1.5h pvin v in 2 .3 v to 5.5v v out 2.8v to 5v 22f 10f adp2503/adp2504 vin vout sw2 fb sync 1 1 allows the adp2503/adp2504 to operate in three different modes. en off on pgnd agnd 0 7475-001 figure 1.
adp2503/adp2504 rev. b | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? typical application circuit ............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 4 ? thermal data ................................................................................ 4 ? thermal resistance ...................................................................... 4 ? esd caution .................................................................................. 4 ? pin configuration and function descriptions ............................. 5 ? typical performance characteristics ............................................. 6 ? theory of operation ...................................................................... 11 ? power save mode ........................................................................ 11 ? soft start ...................................................................................... 11 ? sync function ........................................................................... 11 ? enable ........................................................................................... 11 ? undervoltage lockout ............................................................... 12 ? thermal shutdown .................................................................... 12 ? short-circuit protection ............................................................ 12 ? reverse current limit ............................................................... 12 ? applications information .............................................................. 13 ? inductor selection ...................................................................... 13 ? output voltage programming .................................................. 14 ? pcb layout guidelines .................................................................. 15 ? outline dimensions ....................................................................... 16 ? ordering guide .......................................................................... 16 ? revision history 6/10rev. a to rev. b changes to ordering guide .......................................................... 16 8/09rev. 0 to rev. a changes to features section, figure 1, and general description section ................................................................................................ 1 changes to feedback voltage parameter and en, sync leakage current parameter, table 1 .............................................. 3 changes to table 2 and thermal resistance section ................... 4 added thermal data section ......................................................... 4 changes to figure 2 and table 4 ..................................................... 5 changes to figure 12 ......................................................................... 7 changes to figure 17 ......................................................................... 8 changes to sync function section ............................................ 11 changes to undervoltage lockout section ................................. 12 changes to table 6 .......................................................................... 13 added output voltage programming section ........................... 14 added figure 30; renumbered sequentially .............................. 14 changes to ordering guide .......................................................... 16 10/08revision 0: initial version
adp2503/adp2504 rev. b | page 3 of 16 specifications v in = 3.6 v, v out = 3.3 v, @ t a = t j = ?40c to +125c for minimum/maximum specifications and t a = 25c for typical specifications, unless otherwise noted. 1 table 1. parameters conditions min typ max unit input characteristics input voltage range 2.3 5.5 v undervoltage lockout threshold v in rising 2.15 2.20 2.25 v v in falling 2.10 2.14 2.20 v output characteristics output voltage range 2.8 5.5 v feedback impedance 450 k feedback voltage adp2503/adp2504 adjustable o utput (pwm operation, no load) 490 500 510 mv output voltage initial accuracy adp2503/adp2504 fixe d output (pwm operation, no load) ?2 +2 % load and line regulation v in = 2.3 v to 3.6 v, i load = 0 ma to 500 ma, forced pwm mode 0.5 % v in = 2.3 v to 5.5 v, i load = 0 ma to 500 ma, forced pwm mode 0.6 % current characteristics quiescent current (v in ) i out = 0 ma, v in = en = 3.6 v, device not switching 38 50 a shutdown current t a = t j = ?40c to +125c 0.2 1 a switch characteristics n-channel switches v in = 3.6 v 150 m p-channel switches v in = v out = 3.6 v 150 m p-channel leakage t j = ?40c to +125c 1 a switch current limit adp2504 1.3 2.0 a adp2503 1.0 1.4 a reverse current limit 1.1 a oscillator and startup oscillator frequency 2.1 2.5 2.9 mhz on time pmos1 (buck mode) minimum duty cycle = 30% 130 ns on time nmos2 (boost mode) maximum duty cycle = 50% (2) 200 ns sync clock frequency 2.2 2.8 mhz sync clock minimum off time 160 ns logic level characteristics en, sync input high threshold 1.2 v en, sync input low threshold 0.4 v en, sync leakage current v en = v in , v sync = v in ?1 +0.1 +1 a thermal characteristics thermal shutdown threshold 150 c thermal shutdown hysteresis 25 c 1 all limits at temperature extremes ar e guaranteed via correlation using standard statistical quality control (sqc).
adp2503/adp2504 rev. b | page 4 of 16 absolute maximum ratings table 2. parameter rating pvin, vin, sw1, sw2, vout, sync, en, fb ?0.3 v to +6 v pgnd to agnd ?0.3 v to 0.3 v operating ambient temperature range ?40c to +125c operating junction temperature range ?40c to +125c storage temperature range ?65c to +150c soldering conditions jedec j-std-020 esd human body model 2000 v esd charged device model 1500 v esd machine model 100 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually only, not in combination. the adp2503/adp2504 can be damaged when the junction temperature limits are exceeded. monitoring ambient tempera- ture (t a ) does not guarantee that the junction temperature (t j ) is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. in applications with moderate power dissipation and low pcb thermal resis- tance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. t j of the device is dependent on t a , the power dissipation (p d ) of the device, and the junction-to- ambient thermal resistance ( ja ) of the package. maximum t j is calculated from t a and p d using the following formula: t j = t a + ( p d ja ) ja of the package is based on modeling and calculation using a 4-layer board. the junction-to-ambient thermal resistance is highly dependent on the application and board layout. in applica- tions where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4-layer, 4 inch 3 inch circuit board. refer to jedec jesd 51-9 for detailed information on the board construction. thermal resistance ja are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. package type ja unit 10-lead lfcsp (qfn) 84 c/w esd caution
adp2503/adp2504 rev. b | page 5 of 16 pin configuration and fu nction descriptions 07475-003 notes 1. connect exposed pad to pgnd. 1 vout 2 sw2 3 pgnd 4 sw1 5 pvin 10 fb 9agnd 8vin 7sync 6en top view (not to scale) adp2503/ adp2504 figure 2. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 vout output of the adp2503/adp2504. connect the output capacitor between vout and pgnd. 2 sw2 power switch 2 connection. this is the internal connection to the input pmos and nmos switches. connect sw2 to the inductor with a short, wide track. 3 pgnd power gnd. connect the input and output ca pacitors and the pgnd pin to a pgnd plane. 4 sw1 power switch 1 connection. this is the internal connection to the output pmos and nmos switches. connect sw1 to the inductor with a short, wide track. 5 pvin power input. this the input to the buck-boost power switches. place a 10 f capacitor between pvin and pgnd as close as possible to the adp2503/adp2504. 6 en enable. drive en high to turn on the adp2503/adp2504. bring en low to put the part into shutdown mode. 7 sync the sync pin permits the adp2503/adp2504 to operate in three different modes. normal operation: with sync driven low, the adp 2503/adp2504 operate at 2.5 mhz pwm mode for heavy and medium loads, and moves to power save mode (psm) mode for light loads. forced pwm operation: with sync driven high, the adp2503/adp2504 operate at fixed 2.5 mhz pwm mode for all load conditions. sync mode: to synchronize the adp2503/adp2504 switching to an external signal, drive this pin with a clock between 2.2 mhz and 2.8 mhz. the sync signal must have on and off times greater than 160 ns. 8 vin analog power supply. this is the supply for the adp2503/adp2504 internal circuitry. 9 agnd analog ground. 10 fb output feedback. this is an input to the internal erro r amplifier and must be connected to vout on fixed output versions; for the adjustable mo del, this is the voltage feedback. ep exposed pad connect the exposed pad to pgnd.
adp2503/adp2504 rev. b | page 6 of 16 typical performance characteristics 700 600 500 400 300 200 100 0 output current ( a ) 2.8 2.3 3.3 3.8 4.3 4.8 5.3 input voltage (v) v out = 2.8v v out = 3.5v v out = 4.2v v out = 4.5v v out = 5.0v v out = 3.3v 07475-114 figure 3. adp2503 output current vs. input voltage 1100 1000 900 800 700 600 500 400 300 200 100 0 output current (a) 2.8 2.3 3.3 3.8 4.3 4.8 5.3 input voltage (v) v out = 2.8v v out = 3.3v v out = 3.5v v out = 4.2v v out = 4.5v v out = 5.0v 07475-115 figure 4. adp2504 output current vs. input voltage 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 efficiency (%) 0.1 1 i out (a) 07475-103 v in = 5.5v v in = 4.2v v in = 3.6v v in = 2.3v figure 5. efficiency vs. output current, pwm mode (v out = 5.0 v) 0.001 0.01 0.1 1 100 90 80 70 60 50 40 30 20 10 0 efficiency (%) i out (a) 07475-104 v in = 5.5v v in = 4.2v v in = 3.6v v in = 2.3v figure 6. efficiency vs. output current, psm and pwm mode (v out = 5.0 v) 0.001 0.01 0.1 1 100 90 80 70 60 50 40 30 20 10 0 efficiency (%) i out (a) 07475-109 v in = 5.5v v in = 4.2v v in = 3.6v v in = 2.3v figure 7. efficiency vs. output current, pwm mode (v out = 3.3 v) 0.001 0.01 0.1 1 100 90 80 70 60 50 40 30 20 10 0 efficiency (%) i out (a) 07475-108 v in = 5.5v v in = 4.2v v in = 3.6v v in = 2.3v figure 8. efficiency vs. output current, psm and pwm mode (v out = 3.3 v)
adp2503/adp2504 rev. b | page 7 of 16 0.001 0.01 0.1 1 100 90 80 70 60 50 40 30 20 10 0 efficiency (%) i out (a) 07475-105 v in = 5.5v v in = 4.2v v in = 3.6v v in = 2.3v figure 9. efficiency vs. output current, pwm mode (v out = 2.8 v) 0.001 0.01 0.1 1 100 90 80 70 60 50 40 30 20 10 0 efficiency (%) i out (a) 07475-106 v in = 5.5v v in = 4.2v v in = 3.6v v in = 2.3v figure 10. efficiency vs. output current, psm and pwm mode (v out = 2.8 v) 100 90 80 70 60 50 40 30 20 10 0 2.3 2.8 3.3 efficiency (%) 3.8 4.3 4.8 5.3 v in (v) 07475-107 i out = 500ma i out = 100ma i out = 10ma figure 11. efficiency vs. input voltage (v out = 3.3 v) 3.35 3.33 3.31 3.29 3.27 3.25 0 0.1 0.2 0.3 0.4 0.5 i out (a) v out (v) 0.6 0.7 0.8 0.9 1.0 07475-110 figure 12. load regulation (v in = 3.6 v, v out = 3.3 v) 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.3 2.7 3.1 3.5 frequency (mhz) 3.9 4.3 4.7 5.1 5.5 v in (v) 07475-112 ?40c +25c +85c figure 13. frequency vs. input voltage over temperature (v out = 3.3 v) 50 45 40 35 30 25 20 15 10 5 0 2.3 2.7 3.1 3.5 quiescent current (a) 3.9 4.3 4.7 5.1 5.5 v in (v) 07475-113 figure 14. quiescent current vs. input voltage (v out = 3.3 v)
adp2503/adp2504 rev. b | page 8 of 16 07475-005 ch1 50.0mv b w ch3 5.00v b w ch4 5.00v b w ch2 1.00v b w m40.0s a ch2 3.40mv 4 2 1 3 t 18.20% v in = 3.0v to 3.6v v out = 5.0v v out sw2 sw1 v in figure 15. line transient, pwm mode (v in = 3.0 v to 3.6 v, v out = 5.0 v) 07475-006 ch1 50.0mv b w ch3 5.00v b w ch4 5.00v b w ch2 1.00v b w m40.0s a ch2 3.40v 4 2 3 1 t 18.20% v in = 3.0v to 3.6v v out = 3.3v v out sw2 sw1 v in figure 16. line transient, pwm mode (v in = 3.0 v to 3.6 v, v out = 3.3 v) 07475-007 ch1 50.0mv b w ch3 5.00v b w ch4 5.00v b w ch2 1.00v b w m40.0s a ch2 3.40mv 4 2 3 1 t 18.20% v in = 3.0v to 3.6v v out = 2.8v v out sw2 sw1 v in figure 17. line transient, pwm mode (v in = 3.0 v to 3.6 v, v out = 2.8 v) 07475-008 ch1 100mv b w ch2 250ma ? ch3 5.00v b w ch4 5.00v b w m100s a ch2 60.0ma 1 2 4 3 t 25.80% v in = 3.6v v out = 3.3v sw2 sw1 i out v out figure 18. load transient (v in = 3.6 v, v out = 3.3 v, i out = 100 ma to 350 ma) 07475-111 ch1 100mv b w ch3 5.00v b w ch4 5.00v b w ch2 250ma ? m100s a ch2 60.0ma 4 2 1 3 t 23.00% v in = 3.6v v out = 3.3v sw2 sw1 i out v out figure 19. load transient (v in = 3.6 v, v out = 3.3 v, i out = 10 ma to 300 ma) 07475-010 ch1 100mv b w ch4 2.00v b w ch2 500ma ? m100s a ch2 ?115ma 4 1 2 t 45.40% v in = 3.6v v out = 3.3v sw1 i out v out figure 20. mode change by load transients, load rise (v in = 3.6 v, v out = 3.3 v)
adp2503/adp2504 rev. b | page 9 of 16 07475-011 ch1 100mv b w ch4 2.00v b w ch2 500ma ? m100s a ch2 410ma 4 1 2 t 45.40% v in = 3.6v v out = 3.3v sw1 i out v out figure 21. mode change by load transients, load fall (v out = 3.3 v) 07475-012 ch1 50.0mv b w ch4 5.00v b w ch3 5.00v b w ch2 250ma ? m 400ns a ch3 2.40v 3 4 1 2 t 50.00% v in = 4.0v v out = 3.3v sw2 sw1 i sw v out figure 22. typical pwm switching waveform, buck operation (v out = 3.3 v) 07475-013 ch1 20.0mv b w ch4 5.00v b w ch3 5.00v b w ch2 250ma ? m 400ns a ch4 2.40v 3 1 2 4 t 50.80% v in = 3.0v v out = 3.3v sw2 sw1 i sw v out figure 23. typical pwm switching waveform, boost operation (v out = 3.3 v) 07475-027 ch1 20.0mv b w ch4 5.00v b w ch3 5.00v b w ch2 250ma ? m 400ns a ch4 2.40v 3 1 2 4 t 50.00% v in = 3.0v v out = 3.3v sw2 sw1 i sw v out figure 24. typical pwm switching waveform, buck-boost operation (v out = 3.3 v) 07475-015 ch1 100mv b w ch4 5.00v b w ch3 5.00v b w ch2 1.00a ? m 4.00s a ch2 820ma 3 4 1 2 t 15.20% v in = 3.0v v out = 3.3v sw2 sw1 i sw v out figure 25. typical psm switching waveform, buck-boost operation (v out = 3.3 v) 07475-018 ch1 2.00v b w ch4 5.00v b w ch3 5.00v b w ch2 500ma ? b w m 100s a ch3 2.40v 4 1 3 2 t 9.400% v out = 3.3v en sw1 i sw v out figure 26. startup into pwm mode (v out = 3.3 v, i out = 300 ma)
adp2503/adp2504 rev. b | page 10 of 16 07475-019 ch1 2.00v b w ch4 5.00v b w ch3 5.00v b w ch2 500ma ? b w m 100s a ch3 2.40v 4 1 3 2 t 9.400% v out = 3.3v en sw1 i sw v out figure 27. startup into pwm mode (v out = 3.3 v, i out = 10 ma) 07475-023 ch1 2.00v b w ch4 5.00v b w ch3 5.00v b w ch2 500ma ? b w m 100s a ch3 2.40v 4 1 3 2 t 9.400% v out = 3.3v en sw1 i sw v out figure 28. startup into psm mode (v out = 3.3 v, i out = 10 ma)
adp2503/adp2504 rev. b | page 11 of 16 theory of operation band gap reference sync pgnd agnd en pvin v bat = 2.3v to 5.5v vin vout sw1 sw2 1.5h en 2.25v uvlo 10f 22f adp2503/adp2504 biasing adp2503/adp2504 pmos1 pmos2 nmos1 nmos2 thermal protection pwm control oscillator 8 4 5 6 7 3 9 fb ?0.5v 07475-025 2 1 10 cs soft start figure 29. adp2503/adp2504 block diagram the adp2503/adp2504 are synchronous average current- mode switching buck-boost regulators designed to maintain a fixed output voltage v out from an input supply v in that can be greater than, equal to, or less than v out . when v in is signifi- cantly greater than v out , the device is in buck mode: pmos2 is always active, nmos2 is always off, and the pmos1 and nmos1 switches constitute a buck converter. when v in is significantly lower than v out , the device is in boost mode: pmos1 is always active, nmos1 is always off, and the nmos2 and pmos2 switches constitute a boost converter. when v in is in the range [v out 10%], the adp2503/adp2504 automatically enter the buck-boost mode. in buck-boost mode, the two operations, buck (pmos1 and nmos1 switching in antiphase) and boost (nmos2 and pmos2 switching in antiphase), take place at each period of the clock. this is aimed at maintaining the regulation and keeping a minimal current ripple in the inductor to guaran- tee good transient performances. power save mode when the sync pin is low, the adp2503/adp2504 can operate in power save mode (psm). in this mode, when the load current becomes less than 75 ma nominally at v in = 3.6 v, the control- ler pulls up v out and then halts the switching regime until v out goes back to a restart value. then v out is pulled up again for a new cycle. this minimizes the switching losses at light load. when the load rises above 150 ma, the adp2503/adp2504 revert to fixed pwm mode. this results in about 75 ma of hysteresis between psm and fixed pwm, preventing oscillations between these two modes. soft start when the adp2503/adp2504 are started, v out is ramped from 0 v to its final programmed value in 200 s (typical). this limits the inrush current to less than 600 ma for a nominal output capacitor of 20 f. because the v out start-up slope is constant, the inrush current becomes larger if the output capacitor is made larger. sync function when the sync pin is high, psm is deactivated. the adp2503/ adp2504 always operate in pwm using the internal oscillator. when the sync pin is switching in the 2.1 mhz to 2.9 mhz range, the regulator switching frequency slides to the fre- quency applied on sync and then locks on it. when the sync pin stops switching, the regulator switching frequency slides back to the intern al oscillator frequency. enable the device starts operation with soft start when the en pin is brought high. pulling the en pin low forces the device into shutdown, with a typical shutdown current of 0.2 a. in this mode, the pmos power switches are turned off, the nmos power switches are turned on, and the control circuitry is not enabled. for proper operation, the en pin must be terminated and must not be left floating.
adp2503/adp2504 rev. b | page 12 of 16 undervoltage lockout the undervoltage lockout circuit prevents the device from oper- ating incorrectly at low input voltages. it prevents the converter from turning on the power switches under undefined conditions and, therefore, prevents deep discharge of the battery supply. v in must be greater than 2.25 v to enable the converter. during operation, if v in drops below 2.10 v, the adp2503/adp2504 are disabled until the supply exceeds the uvlo rising threshold. thermal shutdown when the junction temperature, t j , exceeds 150c typical, the device goes into thermal shutdown. in this mode, the power switches are turned off. the device resumes operation when the junction temperature again falls below 125c typical. short-circuit protection when the nominal inductor peak current value of 1.5 a is reached, the adp2503/adp2504 first switch off the nmos2 transistor if it is active. if the current thereafter continues to increase by an extra amount of 200 ma, the pmos1 transistor is also switched off. this operation is reversible when the short circuit stops. it allows the inductor current ripple to be mini- mized close to 1.5 a and, thus, the controller to restore v out even if a high load current is maintained after the short circuit. reverse current limit in case of a short circuit on v out to a value greater than expected, the inductor current becomes negative (reverse current). the negative peak value is limited to 1.1 a by deactivating the pmos2 switch.
adp2503/adp2504 rev. b | page 13 of 16 applications information inductor selection the high 2.5 mhz switching frequency of the adp2503/ adp2504 allows for minimal output voltage ripple, while minimizing inductor size and cost. careful inductor selection also optimizes efficiency and reduces electromagnetic interfe- rence (emi). the selection of the inductor value determines the inductor current ripple and loop dynamics. lfv vvv buckpeaki osc in out in out l ? = ) ( )( , lf v v vv boostpeaki osc in out in out l ? = ) ( )( , where: f osc is the switching frequency (typically 2.5 mhz). l is the inductor value in henries. a larger inductor value reduces the current ripple (and, therefore, the peak inductor current), but is physically larger in size with increased dc resistance. inductor values between 1 h and 1.5 h are suggested. the maximum inductor value to ensure stability is 2.0 h. for increased efficiency with the adp2504, it is suggested that a 1.5 h inductor be used. the inductor peak current is at the maximum in boost mode. to determine the actual maximum inductor current in boost mode, the input dc current should be estimated. v v ii in out max load max in 1 )( )( ? ? ? ? ? ? ? ? = where is efficiency (assume 0.85 to 0.90). the saturation current rating of the inductor must be at least i in(max) + i load /2. ceramic multilayer inductors can be used with lower current designs for a reduced overall solution size and dc resistance (dcr). these are available in low profile packages. care must be taken because these derate quickly as the inductor value is increased, especially at higher operating temperatures. ferrite core inductors have good core loss characteristics as well as reasonable dc resistance. a shielded ferrite inductor reduces the emi generated by the inductor. table 5. sample of recommended inductors vendor value (h) part no. dcr (m) i sat (a) dimensions l w h (mm) toko 1.2 de2810c 55 1.7 2.8 2.8 1.0 toko 1.5 de2810c 60 1.5 2.8 2.8 1.0 toko 1 mdt2520-cn 100 1.8 2.5 2 1.2 murata 1 lqm2hp-g0 55 1.6 2.5 2 1 murata 1.5 lqm2hp-g0 70 1.5 2.5 2 1 tdk 1.0 cpl2512t 90 1.5 2.5 1.5 1.2 tdk 1.5 cpl2512t 120 1.2 2.5 1.5 1.2 coilcraft 1.0 lps3010 85 1.7 3.0 3.0 0.9 coilcraft 1.5 lps3010 120 1.3 3.0 3.0 0.9 taiyo yuden 1.5 nr3015t1 40 1.5 3.0 3.0 1.5 output capacitor selection the output capacitor selection determines the output voltage ripple, transient response, and the loop dynamics of the adp2503/adp2504. the output voltage ripple for a given output capacitor is as follows: () out osc in out in out out cflv vvv buckpeakv ? = 2 8 ) ( )(, osc out out in out load out fvc vvi boostpeakv ? = ) ( )( , if the adp2503/adp2504 are operating in buck mode, the worst-case voltage ripple occurs for the highest input voltage, v in . if the adp2503/adp2504 are operating in boost mode, the worst-case voltage ripple occurs for the lowest input voltage, v in . the maximum voltage overshoot, or undershoot, is inversely proportional to the value of the output capacitor. to ensure stability and excellent transient response, it is recommended to use a minimum of 22 f x5r 6.3 v or 2 10 f x5r 6.3 v capacitors at the output. the effective capacitance (includes temperature and dc bias effects) needed for stability is 14 f. table 6. recommended output capacitors vendor value part no. dimensions l w h (mm) murata 2 10 f, 6.3 v grm188r60j106me47 1.6 0.8 0.8 (2) tdk 2 10 f, 6.3 v c1608jb0j106k 1.6 0.8 0.8 (2) murata 22 f, 6.3 v grm21br60j226me39 2 1.25 1.25 tdk 22 f, 6.3 v c2012x5r0j226m 2 1.25 1.25 tdk 22 f, 10 v c3216x5r1a226k 2 1.25 1.25 murata 2 10 f, 10 v grm21br71a106ke51l 2 1.25 1.25 (2)
adp2503/adp2504 rev. b | page 14 of 16 input capacitor selection the adp2503/adp2504 require an input capacitor to filter noise on the vin pin, and provide the transient currents while maintaining constant input and output voltage. a 10 f x5r/ x7r ceramic capacitor rated for 6.3 v is the minimum recom- mended input capacitor. increased input capacitance reduces the amplitude of the switching frequency ripple on the battery. because of the dc bias characteristics of ceramic capacitors, a 0603, 6.3 v, x5r/x7r, 10 f ceramic capacitor is preferable. table 7. recommended input capacitors vendor value part no. dimensions l w h (mm) murata 10 f, 6.3 v grm188r60j106me47 1.6 0.8 0.8 tdk 10 f, 6.3 v c1608jb0j106k 1.6 0.8 0.8 output voltage programming the adp2503/adp2504 have an adjustable model where the output is programmed through an external resistor divider. the resistor divider is connected between vout and fb and between fb and gnd, and the combined total for the resistor divider should be kept close to 400 k. the typical voltage reference (v ref ) is 500 mv and depending on the output voltage required, the following equation can be used to calculate the value of the resistors: ref out v r rr v ? ? ? ? ? ? ? ? + = 2 21 an example of the calculation for a required output voltage of 3.0 v follows. v5.0 k60 k360 v0.3 ? ? ? ? ? ? ? ? = sw1 1.5h pvin v in 2 .3 v to 5.5v v out 2.8v to 5 v 20f 10f adp2503/adp2504 vin vout sw2 fb r1 r2 sync en off on pgnd agnd 0 7475-101 figure 30. typical application circuit for the adjustable adp2503/adp2504
adp2503/adp2504 rev. b | page 15 of 16 pcb layout guidelines poor layout can affect adp2503/adp2504 performance, caus- ing electromagnetic interference (emi) and electromagnetic compatibility (emc) performance, ground bounce, and voltage losses. poor layout can also affect regulation and stability. a good layout is implemented using the following rules: ? place the inductor, input capacitor, and output capacitor close to the ic using short tracks. these components carry high switching frequencies and large tracks act like antennas. ? route the output voltage path away from the inductor and sw node to minimize noise and magnetic interference. ? maximize the size of ground metal on the component side to help with thermal dissipation. ? use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. 07475-026 figure 31. adp2503/adp2504 evaluation board for fixed output voltages
adp2503/adp2504 rev. b | page 16 of 16 031208-b outline dimensions top view 10 1 6 5 0.30 0.23 0.18 * exposed pad (bottom view) pin 1 index area 3.00 bsc sq seating plane 0.80 0.75 0.70 0.20 ref 0.05 max 0.02 nom 0.80 max 0.55 nom 1.74 1.64 1.49 2.48 2.38 2.23 0.50 bsc p i n 1 i n d i c a t o r ( r 0 . 2 0 ) 0.50 0.40 0.30 * for proper connection of the exposed pad please refer to the pin configuration and function descriptions section of this data sheet. figure 32. 10-lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters ordering guide model 1 voltage max current temperature range package description package option branding adp2503acpz-2.8-r7 2.8 v 0.6 a ?40c to +125c 10-lead lead frame chip scale package [lfcsp_wd] cp-10-9 l9y adp2503acpz-3.3-r7 3.3 v 0.6 a ?40c to +125c 10-lead lead frame chip scale package [lfcsp_wd] cp-10-9 l9z adp2503acpz-3.5-r7 3.5 v 0.6 a ?40c to +125c 10-lead lead frame chip scale package [lfcsp_wd] cp-10-9 lap adp2503acpz-4.2-r7 4.2 v 0.6 a ?40c to +125c 10-lead lead frame chip scale package [lfcsp_wd] cp-10-9 la0 adp2503acpz-4.5-r7 4.5 v 0.6 a ?40c to +125c 10-lead lead frame chip scale package [lfcsp_wd] cp-10-9 la1 adp2503acpz-5.0-r7 5.0 v 0.6 a ?40c to +125c 10-lead lead frame chip scale package [lfcsp_wd] cp-10-9 la2 adp2503acpz-r7 adj 0.6 a ?40c to +125c 10-lead lead frame chip scale packag e [lfcsp_wd] cp-10-9 le7 adp2504acpz-2.8-r7 2.8 v 1 a ?40c to +125c 10-lead le ad frame chip scale package [lfcsp_wd] cp-10-9 l9t adp2504acpz-3.3-r7 3.3 v 1 a ?40c to +125c 10-lead le ad frame chip scale package [lfcsp_wd] cp-10-9 l85 adp2504acpz-3.5-r7 3.5 v 1 a ?40c to +125c 10-lead le ad frame chip scale package [lfcsp_wd] cp-10-9 lan adp2504acpz-4.2-r7 4.2 v 1 a ?40c to +125c 10-lead le ad frame chip scale package [lfcsp_wd] cp-10-9 l9u adp2504acpz-4.5-r7 4.5 v 1 a ?40c to +125c 10-lead le ad frame chip scale package [lfcsp_wd] cp-10-9 l9v adp2504acpz-5.0-r7 5.0 v 1 a ?40c to +125c 10-lead le ad frame chip scale package [lfcsp_wd] cp-10-9 l9w adp2504acpz-r7 adj 1 a ?40c to +125c 10-lead lead frame chip scale packag e [lfcsp_wd] cp-10-9 le8 adp2503cpz-redykit 2 evaluation board for fixed output voltages, 3.3 v and 5.0 v adp2504cpz-redykit 2 evaluation board for fixed output voltages, 2.8 v and 5.0 v 1 z = rohs compliant part. 2 redykit contains two evaluation boards with the stated output voltages plus three devices of each available fixed output volta ge. ?2008C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07475-0-6/10(b)

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